1. Field of the Invention
The present invention relates to an ATM (asynchronous transfer mode) cell assembling/disassembling apparatus provided at an ATM terminal on an ATM network.
2. Description of the Related Art
In general, an ATM cell assembling/disassembling apparatus is provided on an ATM terminal connected to an ATM network. In this ATM cell assembling/disassembling apparatus, as a configuration for realizing a reception function, a 53-byte reception ATM cell sent from a physical layer device is disassembled into a 5-byte header data and 48-byte payload data. Furthermore, from a plurality of payloads, a reception packet is formed per virtual channel (hereinafter, referred to as VC) for use for passing to an upper layer application.
Moreover, for realizing a transmission function, a transmission packet formed by an upper layer application is divided into 48-byte payloads, and a 5-byte header is added to each of the payloads so as to be transmitted to a physical layer device.
FIG. 9 is a block diagram showing a conventional ATM cell assembling/disassembling apparatus. As shown in FIG. 9, an ATM cell assembling/disassembling apparatus 101 is connected to a physical layer device 5 that performs transmission and reception of a frame data to/from an ATM network.
On the other hand, the ATM cell assembling/disassembling apparatus 101 is connected via a host bus 4 to a host CPU 2 for operating an upper layer application and to a host memory 3 for storing a transmission and reception packet. The host CPU 2 also performs management of the host memory 3 and issues commands to the ATM cell assembling/disassembling apparatus 101.
The ATM cell assembling/disassembling apparatus 101 includes: a cell reception/disassembling block 106 for performing cell reception and disassembling; a cell assembling/transmission block 107 for performing assembling of a transmission cell and transmission of the cell; and a reception VC address-transmission/reception parameter storage block 109 for storing information required for transmission and reception.
In general, a semiconductor memory is used for the reception VC address-transmission/reception parameter storage block 109. Moreover, a memory interface block 108 performing memory access control is provided together with the VC address-transmission/reception parameter storage block 109.
The cell reception/disassembly block 106 is constituted by: a reception controller 120 mainly performing a cell reception and cell disassembling; and a reception data buffer 121 for temporarily storing a 48-byte payload data extracted from a cell by the reception controller 120.
The cell assembly/transmission block 107 performing cell assembling and transmission is constituted by transmission controller 125 mainly performing a cell assembling and transmission; and a transmission data buffer 126 for temporarily storing a 48-byte payload data which is used for the cell assembling performed by the transmission controller 125.
Furthermore, the ATM cell assembling/disassembling apparatus 101, for realizing an interface function with a physical layer device, includes: a cell reception interface 110 for receiving an ATM cell from a physical layer device 5, and a cell transmission interface 111 for transmitting an ATM cell to the physical layer device 5.
Moreover, the ATM cell assembling/disassembling apparatus 101 realizes an interface function for the host system by comprising: a host access block 114 for register access from the host CPU 2 and an command to the ATM cell assembling/disassembling apparatus 101; and a DMA output block 112 and a DMA input block 113 for DMA (direct memory access) data transfer to the host memory 3.
FIG. 10 is a flowchart explaining a reception operation by the ATM cell assembling/disassembling apparatus 101. Hereinafter, explanation will be given on the reception operation of the ATM cell assembling/disassembling apparatus 101 shown in FIG. 9, referring to FIG. 10.
When an ATM cell is received from the physical layer device 5 by the cell reception interface 110, the reception controller 120 references a VC identification code VPI/VCI in the 5-byte cell header. According to this VPI/VCI, the reception controller 120 determines whether the received cell belongs to a VC which the upper layer application operating on the host CPU 2 wants to receive (hereinafter, this VC will be referred to as a valid reception VC and the cell will be referred to as a valid reception cell).
The valid reception VC has been stored in the reception VC address-transmission/reception parameter storage block 109.
If the cell passed from the cell reception interface 110 is a valid reception cell, i.e., which VC is stored in the reception VC address-transmission/reception parameter storage block 109, the reception controller 120 determines to perform reception. Moreover, if the cell passed from the cell reception interface 110 is a cell of a VC not stored in the reception VC address-transmission/reception parameter storage block 109, or a cell in which VCI/VPI are all zeros (hereinafter, referred to as an invalid reception cell), the reception controller 120 determines not to perform reception (step S51).
When step S51 has determined to perform reception, the reception controller 120 reads out a reception parameter related to this VC stored in the reception VC address-transmission/reception parameter storage block 109 (step S52), and performs cell disassembling and error detection according to the parameter (step S53). Subsequently, the reception controller 120 stores the 48-byte payload data extracted from the cell, in the reception data buffer 121 and requests the DMA output block 112 to perform DMA transmission of the reception payload data (step S54).
The reception payload data stored in the reception data buffer 121 is DMA-transferred to the host memory 3 by the DMA output block 112 (step S55). This completes one cell reception processing.
It should be noted that if the reception cell is determined to be an invalid reception cell in step S51, the reception controller 120 discards the cell without performing the processes of steps S52 to S55, thus completing one cell reception processing (step S56).
The aforementioned processing is performed each time the cell reception interface 110 receives an ATM cell from the physical layer device 5, and the reception payload data transferred to the host memory 3 is assembled into a packet.
FIG. 11 is a flowchart explaining a transmission operation of the ATM cell assembling/disassembling apparatus 101 of FIG. 9. Hereinafter, explanation will be given on the transmission operation of the ATM cell assembling/disassembling apparatus 101 of FIG. 9, referring to FIG. 11.
Firstly, the transmission controller 125 determines a VC of a cell to be transmitted next according to a transmission rate information of the respective VC, i.e., valid VC (hereinafter, this VC will be referred to as a valid transmission VC and the cell will be referred to as a valid transmission cell). This decision is made for each of the cells and sometimes, in order to adjust the transmission rate, a pseudo cell in which VPI/VCI are all zeroes may be decided to be transmitted (step S61).
Next, the transmission controller 125 branches the processing depending whether the VC determined in step S61 is a valid transmission VC or pseudo cell transmission (step S62).
If the VC determined in step S61 is a valid transmission VC, the transmission controller 125 reads out a transmission parameter of the VC to be transmitted and according to the transmission parameter, determines a storage address of the transmission payload data in the host memory 3. According to this address, the transmission controller 125 requests the DMA input block 113 to DMA-transfer the payload data of one cell from the host memory 3 (step S63).
The DMA input block 113, by the DMA transfer, reads out the transmission payload data of one cell from the host memory 3 and stores the transmission payload data in the transmission data buffer 126 (step S64).
Subsequently, the transmission controller 125 creates a 48-byte transmission payload data. For creation of this transmission payload data, the transmission controller 125 firstly reads out a payload data of one cell from the transmission data buffer 126. If the payload data constitutes an end cell in a packet to be transmitted by the VC, a trailer is added to the payload data entered from the DMA input block 113. If the cell is other than the end cell, the payload data input from the DMA input block 113 is used directly. Furthermore, the transmission controller 125 also creates a 5-byte header. The transmission controller 125 creates a header and a payload and performs CRC calculation and packet length calculation required for trailer creation (step S65)
The transmission controller 125 assembles a cell from the transmission payload data and cell header (step S66).
The cell transmission interface 111 transmits an ATM cell assembled in the transmission controller 125, to the physical layer device 5. Thus, one cell transmission processing is complete (step S67).
If a pseudo cell is decided to be transmitted in step S62, the transmission controller 125 creates a cell data having a cell header in which all the VPI/VCI codes are zeroes (step S68). This data is made into a cell in step S66. The cell transmission interface 111 transmits the assembled ATM cell to the physical layer device 5. Thus, one cell transmission processing is complete (step S67).
In general, in the aforementioned ATM cell assembling/disassembling apparatus, clock is supplied to all the circuits all the time.
Moreover, the aforementioned ATM cell assembling/disassembling apparatus is usually constituted by using the clock synchronization type CMOS semiconductor technique.
The conventional ATM cell assembling/disassembling apparatus shown in FIG. 9 has a problem that power is consumed in vain, because clock is supplied to circuits which are not required for a processing.
More specifically, in the reception operation shown in FIG. 10, if it is decided in step S55 that the cell is not to be received, steps S52 to S55 are skipped. In this case, circuits related to steps S52, S53, S54 in the reception controller 120 need not operate. However, during this time, clock is supplied to these circuits.
Moreover, in the transmission operation shown in FIG. 11, if step S62 determines a pseudo cell transmission, steps S63 and S65 are skipped, but clock is supplied to the circuits related to these processes in the transmission controller 125.
In general, in a clock synchronization type CMOS semiconductor, when a clock is supplied, the power consumption increases in proportion to the clock frequency. And when no clock is supplied, the power consumption can be considered to be zero.
Thus, power is consumed in vain by supplying clock to those circuits which need not operate.
The aforementioned situation will be detailed below. It is assumed that the reception total bit rate of the ATM cell assembling/disassembling apparatus is 156 Mbps. Of the 156 Mbps, 26 Mbps is used by the cell of VC wanted by an upper layer application (this will be referred to as VC1) and VC cell not wanted by the upper layer application is continuously received at the reception rate of 52 Mbps. The remaining 78 Mbps is empty or a pseudo cell is input for rate adjustment.
Here, in steps S52, S53, and S54 in FIG. 10, operation is required only for 26÷156xc3x97100=17% at the most and the remaining 83% does not require clock supply. However, in the conventional ATM cell assembling/disassembling apparatus, clock is supplied even during the time when no VC1 cell is received, and in the circuits performing the steps S52, 53, and 54, 83% of power is consumed in vain.
Moreover, it is assumed that the transmission total bit rate of the ATM cell assembling/disassembling apparatus of FIG. 9 is 156 Mbps. When a transmission data supplied from an upper layer application is transmitted by VC2 at the transmission rate of 26 Mbps, the processes of the steps S63 and S65 need operation only during 26÷156xc3x97100=17% at the most, and the remaining 83% does not need clock supply. However, in the conventional ATM cell assembling/disassembling apparatus, clock is also supplied during the 83% when no VC2 cell is transmitted, and the circuits performing the processes of the steps S63 and S65 consume the 83% power in vain.
As has been described above, in the conventional ATM cell assembling/disassembling apparatus, clock is supplied even to the circuits which need not operate and power is consumed in vain.
It is therefore an object of the present invention to provide an ATM cell assembling/disassembling apparatus capable of reducing a power consumption by interrupting clock supply to circuits which need not operate.
The ATM cell assembling/disassembling apparatus according to the present invention is arranged on an ATM terminal of an ATM network and connected to a physical layer device (5), a host CPU (2), and a host memory (3), said apparatus comprising: cell reception unit (10, 15) for receiving a cell from the physical layer device; reception VC detection unit (16) for deciding whether the reception cell is valid according to a VPI/VCI information in a header of the reception cell; reception control unit (17) for disassembling and error checking the cell which has been decided to be valid by the reception VC detection unit; reception data storage unit (18) for temporarily storing a reception payload data extracted from the reception cell by the reception control unit; and DMA output unit (12) for reading out a reception payload data from the reception data storage unit according to a DMA transfer request from the reception control unit and DMA-transferring the reception payload data to the host memory. The ATM cell assembling/disassembling apparatus further comprises reception clock control unit (20) which starts clock supply to the reception control unit when the reception cell is decided to be valid by the reception VC detection unit, and terminates the clock supply to the reception control unit upon completion of processing for one cell by the reception control unit after the reception control unit performs cell disassembling and error check, stores a reception payload data in the reception data storage unit, and sends a request of a DMA transfer to the DMA output unit.
Moreover, the ATM assembling/disassembling apparatus, as a configuration example, comprises: transmission scheduling unit (21) for deciding a VC for the next cell to be transmitted; transmission control unit (22) for performing DMA transfer request for requesting the transmission payload data of the VC if the VC is decided to be a valid transmission VC, and according to the data fetched by the DMA transfer, creating a transmission payload data and a cell header; payload storage unit (24) for temporarily storing the transmission payload data which has been created by the transmission control unit; transmission header storage unit (25) for temporarily storing the cell header which has been created by the transmission control unit; cell assembling unit (26) for combining the cell header stored in the transmission header storage unit and the transmission payload data stored in the transmission payload storage unit, so as to create a cell; cell transmission unit (11) for transmitting the transmission cell prepared by the cell assembling unit, to the physical layer device; and DMA input unit (13) for reading out the transmission payload data from the host memory according to the DMA transfer request from the transmission control unit, and DMA-transferring the transmission payload data to the transmission control unit. The ATM cell assembling/disassembling apparatus further comprises transmission clock control unit (27) which starts clock supply to the transmission control unit when the transmission scheduling unit has decided to transmit a cell of the valid transmission VC and terminates the clock supply to the transmission control unit after the transmission control unit stores the cell header and the transmission payload data in the transmission header storage unit and the transmission payload storage unit, respectively, thus completing processing for one cell in the transmission control unit.
Moreover, the ATM cell assembling/disassembling apparatus, as a configuration example, comprises: DMA output command storage unit (19a) for storing the DMA transfer request issued as a command from the reception control unit; and DMA output clock control unit (60) which starts clock supply to the DMA output unit when the number of commands stored in the DMA output command storage unit has become one or more and terminates the clock supply to the DMA output unit if the number of commands stored in the DMA output command storage unit is 0 when DMA transfer of one command is completed by the DMA output unit. The DMA output unit (12a) operates according to the clock, reads out a command from the DMA output command storage unit and performs DMA transfer according to the command which has been read out.
Moreover, the ATM cell assembling/disassembling apparatus, as a configuration example, comprises: DMA input command storage unit (23a) for storing the DMA transfer request issued as a command from the transmission control unit; and DMA input clock control unit (61) which starts clock supply to the DMA input unit when the number of commands stored in the DMA input command storage unit has become one or more and terminates the clock supply to the DMA input unit if the number of commands stored in the DMA input command storage unit is 0 when DMA transfer of one command is completed by the DMA input unit. The DMA input unit (13a) operates according to the clock, reads out a command from the DMA input command storage unit and performs DMA transfer according to the command which has been read out.
Moreover, the reception control unit (17b) outputs a write-in signal (82) indicating that a reception payload data is being written into the reception data storage unit (18); and the DMA output unit (12b) outputs a read-out signal (81) indicating that a reception payload data is being read out from the reception data storage unit. The ATM cell assembling/disassembling apparatus further comprises reception data storage clock control unit (80) which, referencing the write-in signal and the read-out signal, supplies a write-in clock to the reception data storage unit only if the write-in signal indicates that a data is being written in and supplies a read-out clock to the reception data storage unit only if the read-out signal indicates that a data is being read out.
Moreover, the transmission control unit (22b) outputs a write-in signal (91) indicating that a transmission payload data is being written into the transmission payload storage unit (24); and the cell assembling unit (26b) outputs a read-out signal (92) indicating that a transmission payload data is being read out from the transmission payload storage unit. The ATM cell assembling/disassembling apparatus further comprises transmission payload storage clock control unit (90) which references the write-in signal and the read-out signal and supplies a write-in clock to the transmission payload storage unit only if the write-in signal indicates that a data is being written in, and supplies a read-out clock to the transmission payload storage unit only if the read-out signal indicates that a data is being read out.